computer science assignment

A4.1

Given the following sequences of events, show which routines the CPU is executing for times 0 to 100 ms. Each handler routine (with interrupt request) takes 20 ms to complete.

a) Time       Action    0 ms     Start of main program 10 ms      IRQ0 20 ms      IRQ1 45 ms      IRQ2 60 ms      IRQ3

b) Time       Action    0 ms     Start of main program 10 ms      IRQ1 20 ms      IRQ0 45 ms      IRQ3 60 ms      IRQ2

IRQ n has the lowest priority; IRQ0 has the highest priority

Obs:

If IRQi is coming in the period of execution of IRQj and j has higher priority, then IRQi is postponed until IRQj is finished.

If IRQi is coming in the period of execution of IRQj and i has higher priority, then IRQi is started and IRQj is temporally suspended until IRQi is finished.

a)

Routine	Main		IRQ0		IRQ1					IRQ2			IRQ3
	0	5	10	15	20	25	30	35	40	45	50	55	60	65	70	75	80	85	90	95	100
Main
IRQ0
IRQ1
IRQ2
IRQ3

b)

Routine	Main		IRQ1		IRQ0					IRQ3			IRQ2
	0	5	10	15	20	25	30	35	40	45	50	55	60	65	70	75	80	85	90	95	100
Main
IRQ1
IRQ0
IRQ3
IRQ2

A4.2

Consider a CPU that does not implement scalar pipeline processing with an instruction cycle of:

·         a one clock-cycle fetch

·         a two clock-cycle decode

·         a three clock-cycle execute

How many clock cycles would be required for a 100 instruction sequence?

A4.3

Present the main characteristics of the RISC CPU and CISC CPU (regarding bank of registers, format instructions, parallel computations, register-oriented instructions, superscalar processing)

Presents the RISC CPU differs from the CISC CPU

Which type of processor is x86 CPU 

Mark with “YES” the characteristics of the RISC CPU

Characteristics	RISC CPU
Uses reduced instruction only
Uses a large bank of registers
Uses fixed length and fixed format instructions
Uses complex instructions
Performs parallel computations
Uses register-oriented instructions
Uses superscalar processing
Uses limited addressing modes
Uses pipelining
Has a limited and simple instruction set

A4.4

Present the x86 general-purpose registers

A4.5

Make a comparison regarding the speed and price between:

Ø       Level 1 Cache

Ø       Level 2 Cache

Ø       Main memory

Ø       Registers

Ø       Virtual memory

A4.6

Consider a RAM chip of 1M words x 32 bits/word that has Read and Write inputs. 

                a.             How many address lines are needed to access the chip? 

                b.             How many data lines are needed to access the chip?

c.             Draw a block diagram and label all pins (lines) that are required for the RAM integrated circuit as input, output, or input/output.

A4.7

Write code that performs the computation:

                                X = A + B * C + D / E* F

using CPUs that have the following instruction formats:   stack instructions

A4.8

Consider a CPU that can address 4M words x 32 bits/word of memory.

1.        Show the layout of an associative cache that can hold

                256K words x 32 bits/word.

2.        Show the layout of a two-way set-associative cache that can hold

                256K words x 32 bits/word

A4.9

Match the descriptions below with the most appropriate memory management scheme (A through E).  Answers may be used once, more than once, or not at all.

                A.            Fixed-partition multiprogramming

                B.            Single task system

                C.            Variable-partition multiprogramming

                D.            Virtual memory system with paging

                E.             Virtual memory system with segmentation

_______ a) contiguous allocation of memory in regions whose size cannot be varied

_______ b) contiguous allocation of memory where region size can be varied dynamically

_______ c) contiguous allocation of memory where holes are created as programs are moved in and out of memory

_______ d) programs are loaded into memory using a best-fit, first-fit, or largest-fit algorithm

_______ e) not capable of multitasking

_______ f) non-contiguous allocation of equal-sized blocks

_______ g) non-contiguous allocation of unequal-sized blocks

A4.10

A computer system has 16K of memory, a segmented Memory Management Unit, and the following segment table (with all numbers in hexadecimal):

Logical Address	Physical Start	Physical Size
0	800	100
1000	1000	100
2000	2600	150
3000	600	50
4000	2800	50
5000	0	100
6000	1200	125
7000	1800	150
8000	1400	150
9000	1600	50
A000	2000	150
B000	2200	100
C000	2400	125
D000	200	125
E000	3000	50
F000	400	150

1.        Indicate the physical memory location corresponding to logical address 8020.

2.        Indicate the logical address corresponding to physical memory location 1220.